Local area networks use a network cable or other network media to link nodes (e.g., workstations, routers and switches) to the network. Each local area network architecture uses a media access control (MAC) enabling network interface device at each network node to share access to the media.
Physical (PHY) layer devices are configured for translating digital packet data received from a MAC across a standardized interface, e.g., a Media Independent Interface (MII), into an analog signal for transmission on the network medium, and reception of analog signals transmitted from a remote node via the network medium. An example is the 100BASE-TX Ethernet (IEEE Standard 802.3u) receiver, configured for receiving a three-level MLT-3 encoded analog signal at a 125 Mb/s data rate.
One problem with transmission of analog signals on the network medium is attenuation of high-frequency components. An MLT-3 encoded signal transmitted by the network medium encounter transmission loss in the form of high-frequency attenuation. Hence, the 100-BASE-TX Ethernet (IEEE 802.3u) receiver includes a line equalizer having a high-pass filter to compensate for the high-frequency attenuation from the network medium.
FIG. 1 is a circuit diagram illustrated an exemplary network active line equalizer 80 having a single zero high-pass filter 20. Transistors 28a and 28b, functioning as resistors, together with capacitors 30a and 30b comprise a single zero impedance circuit which connects first and second MOS transistors at corresponding first junctions N1 and N2. Transistors 28a and 28b (resistors) are PMOS devices. The characteristic of the high-pass filter can be easily changed by changing resistor value, e.g. changing the size of the MOS device. For example, the gate voltage of the devices 28a and 28b may be changed by varying the voltage of the control signal CONTROL. Varying the gate voltage of transistors 28a and 28b changes the effective resistance.
As shown in FIG. 1, bias current (I.sub.B1 and I.sub.B2) is supplied to transistors 32a, 32b, 34a and 34b for generating a bias current to nodes N1 and N2, respectively. Specifically, current flows into transistors 60 and 62 which is reflected into the MOS transistor pairs 32a, 32b and 34a, 34b. The pair of transistors 32a and 32b output the bias current I.sub.B1 to node N1 and transistors 34a and 34b output the bias current I.sub.B2 to node N2 (I.sub.B1 =I.sub.B2). The MOS transistors 22 and 24 output differential currents having a difference corresponding to the impedance of MOS transistors 28a, 28b and 30a, 30b, and the differential input signals V1 and V2. The current mirror transistor 36 has a match, namely MOS transistor 42, that attempts to mirror the current of MOS transistor 36. Similarly, current mirror transistor 38 is matched by MOS transistor 46. Hence, the current in MOS transistor 36 will be reproduced in MOS transistor 42 and the current in MOS transistor 38 will be reproduced in MOS transistor 46. The current in MOS transistor 42 is dropped across load transistors 40a, 40b and 40c, converting the current to the output voltage V.sub.01. Similarly, the current in MOS transistor 46 is dropped across load transistors 48a, 48b and 48c, producing a voltage drop that converts the current to output voltage V.sub.02. In addition, the resistance values can be easily changed, either by changing the size of the MOS devices, or by individually controlling each of the MOS devices 40a, 40b, 40c, 48a, 48b and 48c.
The poles and zeros of most active line equalizers depend on precise values of resistance and capacitance used in the circuit. However, such precision is not possible with most semiconductor manufacturing processes due to process gradients, and temperature and power supply variations resulting from resistance, and to a certain extent, capacitance. However, a majority of the variation comes from transistor transconductance Gm (1/resistance).
A popular method of process and temperature compensation for Gm and capacitance variations is using a PLL (phase locked loop). In a PLL, a voltage controlled oscillator (VCO) is used to generate both a clock based on a Gm and capacitance C (of a device) which must be maintained, and a certain amount of current which is used to charge and discharge the Gm and C. This clock is referenced to an external fixed clock. If any change in the Gm or C occurs, the clock generated by the VCO will shift both in phase and frequency relative to the incoming fixed clock. The PLL will then adjust the Gm of the device to compensate for the change and synchronize the VCO to the incoming clock.
As PLL circuits are quite large compared to network line equalizers, the disadvantage of the method of using a PLL is that it requires an entire PLL to be formed on the chip to compensate the network line equalizer and the PLL circuit would occupy a larger area of the chip than that of the network line equalizer. This is not an efficient use of chip area. Furthermore, a PLL circuit is complicated to implement as additional simulation is needed to verify the functionality and stability of the PLL.